CDCE62005 datasheet(63/85 Pages) TI1

Part #	CDCE62005

Description	3:5 Clock Generator

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Manufacturer	TI1 [Texas Instruments]

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CDCE62005

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SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

8.6.3 Device Registers: Register 2 Address 0x02

Table 42. CDCE62005 Register 2 Bit Definitions

RAM BIT

BIT NAME

BLOCK

0

REFDIV0

Reference Divider Bit 0

EEPROM

Reference

Divider

1

REFDIV1

Reference Divider Bit 1

EEPROM

2

RESERVED

Must be set to 0

EEPROM

3

RESERVED

Must be set to 0

EEPROM

4

OUTMUX2SELX

Output 2

OUTPUT MUX 2 Select. Selects the Signal driving Output Divider 2

EEPROM

(X,Y) = 00: PRI_REF, 01:SEC_REF, 10:SMART_MUX, 11:VCO_CORE

5

OUTMUX2SELY

Output 2

EEPROM

6

PH2ADJC0

Output 2

EEPROM

7

PH2ADJC1

Output 2

EEPROM

8

PH2ADJC2

Output 2

EEPROM

9

PH2ADJC3

Output 2

Coarse phase adjust select for output divider 2

EEPROM

10

PH2ADJC4

Output 2

EEPROM

11

PH2ADJC5

Output 2

EEPROM

12

PH2ADJC6

Output 2

EEPROM

13

OUT2DIVRSEL0

Output 2

EEPROM

14

OUT2DIVRSEL1

Output 2

EEPROM

15

OUT2DIVRSEL2

Output 2

EEPROM

16

OUT2DIVRSEL3

Output 2

OUTPUT DIVIDER 2 Ratio Select

EEPROM

17

OUT2DIVRSEL4

Output 2

EEPROM

18

OUT2DIVRSEL5

Output 2

EEPROM

19

OUT2DIVRSEL6

Output 2

EEPROM

When set to 0, the divider is disabled

20

OUT2DIVSEL

Output 2

EEPROM

When set to 1, the divider is enabled

High Swing LVPECL When set to 1 and Normal Swing when set to 0.

– If LVCMOS or LVDS is selected the Output swing will stay at the same level.

(1)

21

HiSWINGLVPEC2

Output 2

EEPROM

– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to 1 and Normal LVPECL if

it is set to 0.

22

CMOSMODE2PX

Output 2

LVCMOS mode select for OUTPUT 2 Positive Pin.

EEPROM

(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State

23

CMOSMODE2PY

Output 2

EEPROM

24

CMOSMODE2NX

Output 2

LVCMOS mode select for OUTPUT 2 Negative Pin.

EEPROM

(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State

25

CMOSMODE2NY

Output 2

EEPROM

26

OUTBUFSEL2X

Output 2

OUTPUT TYPE

RAM BITS

EEPROM

22

23

24

25

26

27

LVPECL

0

1

LVDS

0

1

0

1

27

OUTBUFSEL2Y

Output 2

EEPROM

LVCMOS

See Settings Above

0

Output Disabled

0

1

0

1

0

* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs

(1)

Set the R2.21 to 0 for LVDS and LVCMOS outputs

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