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CDCE62005 Datasheet(PDF) 62 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 62 Page - Texas Instruments |
62 / 85 page CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com 8.6.2 Device Registers: Register 1 Address 0x01 Table 41. CDCE62005 Register 1 Bit Definitions RAM BIT BIT NAME RELATED DESCRIPTION/FUNCTION BLOCK 0 DIV2SECX Pre-Divider Selection for the Secondary Reference EEPROM Secondary (X,Y)=00:3-state, 01:Divide by 1, 10:Divide by 2, 11:Reserved Reference 1 DIV2SECY EEPROM 2 RESERVED Must be set to 0 EEPROM 3 RESERVED Must be set to 0 EEPROM 4 OUTMUX1SELX Output 1 OUTPUT MUX 1 Select. Selects the Signal driving Output Divider 1. EEPROM (X,Y) = 00: PRI_REF, 01:SEC_REF, 10:SMART_MUX, 11:VCO_CORE 5 OUTMUX1SELY Output 1 EEPROM 6 PH1ADJC0 Output 1 EEPROM 7 PH1ADJC1 Output 1 EEPROM 8 PH1ADJC2 Output 1 EEPROM 9 PH1ADJC3 Output 1 Coarse phase adjust select for output divider 1 EEPROM 10 PH1ADJC4 Output 1 EEPROM 11 PH1ADJC5 Output 1 EEPROM 12 PH1ADJC6 Output 1 EEPROM 13 OUT1DIVRSEL0 Output 1 EEPROM 14 OUT1DIVRSEL1 Output 1 EEPROM 15 OUT1DIVRSEL2 Output 1 EEPROM 16 OUT1DIVRSEL3 Output 1 OUTPUT DIVIDER 1 Ratio Select EEPROM 17 OUT1DIVRSEL4 Output 1 EEPROM 18 OUT1DIVRSEL5 Output 1 EEPROM 19 OUT1DIVRSEL6 Output 1 EEPROM When set to 0, the divider is disabled 20 OUT1DIVSEL Output 1 EEPROM When set to 1, the divider is enabled High Swing LVPECL When set to 1 and Normal Swing when set to 0 – If LVCMOS or LVDS is selected the Output swing will stay at the same level. (1) 21 HiSWINGLVPECL1 Output 1 EEPROM – If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to 1 and Normal LVPECL if it is set to 0. 22 CMOSMODE1PX Output 1 LVCMOS mode select for OUTPUT 1 Positive Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State 23 CMOSMODE1PY Output 1 EEPROM 24 CMOSMODE1NX Output 1 LVCMOS mode select for OUTPUT 1 Negative Pin. EEPROM (X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State 25 CMOSMODE1NY Output 1 EEPROM 26 OUTBUFSEL1X Output 1 OUTPUT TYPE RAM BITS EEPROM 22 23 24 25 26 27 LVPECL 0 0 0 0 0 1 LVDS 0 1 0 1 1 1 27 OUTBUFSEL1Y Output 1 EEPROM LVCMOS See Settings Above* 0 0 Output Disabled 0 1 0 1 1 0 * Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs (1) Set the R1.21 to 0 for LVDS and LVCMOS outputs 62 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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