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CDCE62005 Datasheet(PDF) 59 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 59 Page - Texas Instruments |
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59 / 85 page  SPI_CLK SPI_MOSI SPI_MISO SPI_LE Bit30 Bit31 Bit0=0 Bit1 Bit 0 Bit 1 Bit 29 Bit 30 Bit 31 SPI _ MOSI SPI _ CLK SPI _ LE SPI_CLK SPI_MOSI SPI_MISO SPI_LE SPIMaster SPISlave CDCE62005 www.ti.com SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 8.5.1.4 SPI Consecutive Read/Write Cycles to the CDCE62005 Figure 42 illustrates how two consecutive SPI cycles are performed between a SPI Master and the CDCE62005 SPI Slave. Figure 42. Consecutive Read/Write Cycles 8.5.1.5 Writing to the CDCE62005 Figure 43 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit 0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE62005, data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE62005 that the transmission of the last bit in the stream (Bit 31) has occurred. Figure 43. CDCE62005 SPI Write Operation 8.5.1.6 Reading from the CDCE62005 Figure 44 shows how the CDCE62005 executes a Read Command. The SPI master first issues a Read Command to initiate a data transfer from the CDCE62005 back to the host (see Table 40). This command specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE62005 resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the CDCE62005 presents the data present in the register specified in the Read Command on SPI_MISO. Figure 44. CDCE62005 Read Operation Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 59 Product Folder Links: CDCE62005 |
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