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CDCE62005 Datasheet(PDF) 58 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 58 Page - Texas Instruments |
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58 / 85 page  SPI_CLK SPI_MOSI SPI_LE SPI_MISO SPI_LE SPI_CLK SPI_MOSI SPI_MISO SPI _ CLK SPI _ MOSI SPI _ MISO SPI _ LE CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com The CDCE62005 on-board EEPROM has been factory preset to the default settings listed in Table 39. Table 39. Register and Default Setting REGISTER DEFAULT SETTING REG0000 8184032 REG0001 8184030 REG0002 8186030 REG0003 EB86030 REG0004 0186031 REG0005 101C0BE REG0006 04BE19A REG0007 BD0037F The Default configurations programmed in the device is set to: Primary and Secondary are set to LVPECL ac- coupled termination and the Auxiliary input is enabled. The Smart Mux is set to auto select among Primary, Secondary and Auxiliary. Reference is set at 25MHz and the dividers are selected to run the VCO at 1875MHz. • Output 0 & 1 are set to output 156.25MHz with LVPECL signaling • Output 2 is set to output 125MHz/ LVPECL • Output 3 is set to output 125MHz/ LVDS • Output 4 is set to output 125MHz/ LVCMO 8.5.1.3 SPI Interface Master The Interface master can be designed using a FPGA or a micro controller. The CDCD62005 acts as a slave to the SPI master. The SPI Master should be designed to issue none consecutive read or write commands. The SPI clock should start and stop with respect to the SPI_LE signal as shown in Figure 41. SPI_MOSI, SPI_CLK, and SPI_LE are generated by the SPI Master. SPI_MISO is gnererated by the SPI slave the CDCE62005. Figure 41. CDCE62005 SPI Read/Write Command 58 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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