CDCE62005 datasheet(56/85 Pages) TI1

Part #	CDCE62005

Description	3:5 Clock Generator

PDF	85 Pages

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Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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56 / 85 page

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Address

Bits

(4)

Lastin /

Lastout

FirstIn /

FirstOut

SPI _LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPIMaster (Host)

SPI _LE

SPI _CLK

SPI_MOSI

SPI_MISO

SPISlave (CDCE 62005)

DeviceRegisterN

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SPIRegister

DataBits (28)

CDCE62005

SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

www.ti.com

Programming (continued)

Figure 40. CDCE62005 SPI Communications Format

8.5.1.2 CDCE62005 SPI Command Structure

The CDCE62005 supports four commands issued by the Master via the SPI:

•

Write to RAM

•

Read Command

•

Copy RAM to EEPROM – unlock

•

Copy RAM to EEPROM – lock

Table 38 provides a summary of the CDCE62005 SPI command structure. The host (master) constructs a Write

to RAM command by specifying the appropriate register address in the address field and appends this value to

the beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first.

The host must issue a Read Command to initiate a data transfer from the CDCE62005 back to the host. This

command specifies the address of the register of interest in the data field.

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