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CDCE62005 Datasheet(PDF) 55 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 85 page  Device Registers Interface & Control Smart MUX Frequency Synthesizer Output Channel 1 Output Channel 2 Output Channel 3 Output Channel 4 Output Channel 0 EEPROM Input Block Synthesizer Block OutputBlocks Interface & Control Block ToSatellite System Components RecoveredClock CleanedClock SERDES Start-up/ Back -up Clock CDCE62005 www.ti.com SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 the SERDES recovers the clock, the CDCE62005 removes the jitter via the on-chip synthesizer/loop filter. The recovered clock from the communications link becomes the frequency reference for the satellite system after the smart multiplexer automatically switches over to it. The CDCE62005 applies the cleaned clock to the recovered clock input on the SERDES, thereby establishing a reliable communications link between host and satellite systems. Figure 39. CDCE62005 SERDES Startup Mode 8.5 Programming 8.5.1 Interface and Control Block The Interface and Control Block includes a SPI interface, three control pins, a non-volatile memory array in which the device stores default configuration data, and an array of device registers implemented in Static RAM. This RAM, also called the device registers, configures all hardware within the CDCE62005. 8.5.1.1 Serial Peripheral Interface (SPI) The serial interface of CDCE62005 is a simple bidirectional SPI interface for writing and reading to and from the device registers. It implements a low speed serial communications link in a master/slave topology in which the CDCE62005 is a slave. The SPI consists of four signals: SPI_CLK: Serial Clock (Output from Master) The CDCE62005 clocks data in and out on the rising edge of SPI_CLK. Data transitions therefore occur on the falling edge of the clock. SPI_MOSI: Master Output Slave Input (Output from Master) SPI_MISO: Master Input Slave Output (Output from Slave) SPI_LE: Latch Enable (Output from Master) The falling edge of SPI_LE initiates a transfer. If SPI_LE is high, no data transfer can take place. The CDCE62005 implements data fields that are 28-bits wide. In addition, it contains 9 registers, each comprising a 28 bit data field. Therefore, accessing the CDCE62005 requires that the host program append a 4- bit address field to the front of the data field as follows: Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 55 Product Folder Links: CDCE62005 |
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