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CDCE62005 Datasheet(PDF) 53 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 53 Page - Texas Instruments

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6.02
1.76
=
+
ADC
SNR
N
(
)
(
)
2
2
=
+
total
ADC
CLK
jitter
jitter
jitter
10
1
20 log
2
é
ù
=
ê
ú
ë
û
jitter
in
total
SNR
πf jitter
Output
Divider 0
Output
Divider 1
Output
Divider 2
Output
Divider 3
Output
Divider 4
PFD/
CP
/1:/2:HiZ
/1:/2:HiZ
Prescaler
Feedback
Divider
Input
Divider
Reference
Divider
30.72 MHz
10.00 MHz
122 .88 MHz
491 .52 MHz
245 .76 MHz
30.72 MHz
30.72 MHz
10 MHz
10 MHz
CDCE62005
www.ti.com
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
Device Functional Modes (continued)
Table 37. Clock Frequencies
CLOCK FREQUENCY
INPUT/OUTPUT
FORMAT
NUMBER
CDCE62005 PORT
COMMENT
10.000 MHz
Input
LVDS
1
SEC_REF
Low end crystal oscillator
30.72 MHz
Input
LVDS
1
PRI_REF
Reference from backplane
122.88 MHz
Output
LVDS
1
U0
SERDES Clock
491.52 MHz
Output
LVPECL
1
U1
ASIC
245.76 MHz
Output
LVPECL
1
U2
FPGA
30.72 MHz
Outputs
LVCMOS
2
U3
ASIC
10.000 MHz
Outputs
LVCMOS
2
U4
CPU, DSP
Figure 36. CDCE62005 Jitter Cleaner Example
8.4.3.1 Clocking ADCs with the CDCE62005
High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample
clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly
implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation
trend often causes engineers working in communications system design to encounter the term clock limited
performance. Therefore, it is important to understand the impact of clock jitter on ADC performance. Equation 14
shows the relationship of data converter signal to noise ratio (SNR) to total jitter.
(14)
Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample
clock:
(15)
With respect to an ADC with N-bits of resolution, ignoring total jitter, DNL, and input noise, the following equation
shows the relationship between resolution and SNR:
(16)
Copyright © 2008–2015, Texas Instruments Incorporated
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