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CDCE62005 Datasheet(PDF) 52 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
PDF  85 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 52 Page - Texas Instruments

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XTAL /
AUX IN
Output
Divider 0
U0P
U0N
PFD/
CP
Prescaler
Feedback
Divider
Input
Divider
Smart
MUX
Output
Divider 4
U4P
U4N
/1 - /80
U0P
U0N
PRI_REF
SEC_REF
/1 - /80
U4P
U4N
Divide by 1: Up to 1500 MHz
Otherwise : Up to 1175 MHz
Up to 5 Outputs :
LVPECL or LVDS
Up to 10 Outputs:
LVCMOS
CDCE62005
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
www.ti.com
8.4 Device Functional Modes
8.4.1 Fan-Out Buffer
Each output of the CDCE62005 can be configured as a fan-out buffer (divider bypassed) or fan-out buffer with
divide and skew control functionality.
Figure 34. CDCE62005 Fan-out Buffer Mode
8.4.2 Clock Generator
The CDCE62005 can generate 5–10 low noise clocks from a single crystal as follows:
Figure 35. CDCE62005 Clock Generator Mode
8.4.3 Jitter Cleaner – Mixed Mode
The following table presents a common scenario. The CDCE62005 must generate several clocks from a
reference that has traversed a backplane. In order for jitter cleaning to take place, the phase noise of the on-
board clock path must be better than that of the incoming clock. The designer must pay attention to the
optimization of the loop bandwidth of the synthesizer and understand the phase noise profiles of the oscillators
involved. Further, other devices on the card require clocks at frequencies not related to the backplane clock. The
system requires combinations of differential and single-ended clocks in specific formats with specific phase
relationships.
NOTE
Pay special attention when using the universal inputs with two different clock sources. Two
clocks derived from the same source may use the internal bias generator and internal
termination network without jitter performance degradation. However, if their origin is from
different sources ( two independent oscillators, for example) then sharing the internal bias
generator can degrade jitter performance significantly.
52
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Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: CDCE62005


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