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CDCE62005 Datasheet(PDF) 50 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 50 Page - Texas Instruments |
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50 / 85 page  CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com Table 35. VCO Calibration Method Through Register Programming ENCAL_MODE VCO CALIBRATION MECHANISM(1) REMARKS Bit 6.27 1 VCO calibration starts at ENCAL bit (Register 6 bit 22) The outputs turn off for the duration of the calibration, which toggling low-to-high. are a few ns. This implementation is recommended when the VCO needs to be re-calibrated quickly after a PLL setting was changed. No device block is powered down during this calibration. 0 Device is powered down when SLEEP bit (Register 8 bit All outputs are disabled while SLEEP bit is zero. This 7) is toggle 1-to-0. After asserting SLEEP from zero to implementation is an alternative implementation to option one the VCO becomes calibrated. one. It takes a longer duration, as all device blocks are powered down while SLEEP is low. (1) A VCO calibration is also initiated if the external PD pin is toggle high-low-high and the ENCAL_MODE bit (Register 6 bit 27) is preset to 0. In this case all EEPROM registers become reloaded into the device. 8.3.9 Startup Time Estimation The CDCE62005 startup time can be estimated based on the parameters defined in Table 36 and graphically shown in Figure 32. See also CDCE62005 SERDES Startup Mode. Table 36. Startup Time Dependencies PARAMETER DEFINITION DESCRIPTION METHOD OF DETERMINATION tpul Power-up time (low Power-supply rise time to low limit of Power On Reset Time required for power supply to ramp limit) (POR) trip point to 2.27 V tpuh Power-up time (high Power-supply rise time to high limit of Power On Reset Time required for power supply to ramp limit) (POR) trip point to 2.64 V trsu Reference start-up After POR releases, the Colpitts oscillator is enabled. 500 µs best-case and 800 µs worst-case time This start-up time is required for the oscillator to (This is only for crystal connected to generate the requisite signal levels for the delay block AUX IN) to be clocked by the reference input tdelay Delay time Internal delay time generated from the clock. This delay tdelay = 16384 x tid provides time for the oscillator to stabilize. tid = period of input clock to the input divider tVCO_CAL VCO calibration time VCO calibration time generated from the PFD clock. tVCO_CAL = 550 x tPFD This process selects the operating point for the VCO tPFD = period of the PFD clock based on the PLL settings. tPLL_LOCK PLL lock time Time required for PLL to lock within ±10 ppm of tPLL_LOCK = 3/LBW reference frequency LBW = PLL Loop Bandwidth Figure 32. Start-up Time Dependencies 50 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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