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CDCE62005 Datasheet(PDF) 31 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
Download  85 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 31 Page - Texas Instruments

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360
Stepsize(deg) =
= 22.5 /Step
16
o
/1 - /80
Digital Phase Adjust (7-bits)
Clock
IN
(from Output MUX)
To Output Buffer
Clock IN
Output Divider (no adjust )
Output Divider (phase adjust )
Start Divider
1
(
)
f
=
ClockIN
Stepsize sec
OutputDivideRatio
360
(
) =
degrees
Stepsize deg
OutputDivideRatio
CDCE62005
www.ti.com
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
8.3.5.11 Digital Phase Adjust
Figure 25 provides an overview of the Digital Phase Adjust feature. The output divider includes a coarse phase
adjust that shifts the divided clock signal that drives the output buffer. Essentially, the Digital Phase Adjust timer
delays when the output divider starts dividing; thereby shifting the phase of the output clock. The phase adjust
resolution is a function of the divide function. Coarse phase adjust parameters include:
Number of phase delay steps the number of phase delay steps available is equal to the divide ratio selected.
For example, if a Divide by 4 is selected, then the Digital Phase Adjust can be programmed
to select when the output divider changes state based upon selecting one of the four counts
on the input. Figure 25 shows an example of divide by 16 in which there are 16 rising edges
of Clock IN at which the output divider changes state (this particular example shows the
fourth edge shifting the output by one fourth of the period of the output).
Phase delay step size the step size is determined by the number of phase delay steps according to the
following equations:
(5)
(6)
Figure 25. CDCE62005 Phase Adjust
8.3.5.12 Phase Adjust Example
Given:
Output Frequency = 30.72 MHz
VCO Operating Frequency = 1966.08 MHz
Prescaler Divider Setting = 4
Output Divider Setting = 16
(7)
8.3.5.13 Valid Register Settings for Digital Phase Adjust Blocks
Table 14 through Table 19 provide a list of valid register settings for the digital phase adjust blocks.
Copyright © 2008–2015, Texas Instruments Incorporated
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