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CDCE62005 Datasheet(PDF) 28 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 85 page  CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com 8.3.5.7 Output Multiplexer Control The Clock Divider Module receives the clock selected by the output multiplexer. The output multiplexer selects from one of four clock sources available on the Internal Clock Distribution. For a description of PRI_REF, SEC_REF, and SMART_MUX, see Figure 18. For a description of SYNTH, see Figure 28. Table 10. CDCE62005 Output Multiplexer Control Settings OUTPUT MULTIPLEXER CONTROL REGISTER n (n = 0,1,2,3,4) CLOCK SOURCE SELECTED OUTMUXnSELX OUTMUXnSELY n.4 n.5 0 0 PRI_REF 0 1 SEC_REF 1 0 SMART_MUX 1 1 SYNTH 8.3.5.8 Output Buffer Control Each of the five output channels includes a programmable output buffer; supporting LVPECL, LVDS, and LVCMOS modes. Table 11 lists the settings required to configure the CDCE62005 for each output type. Registers 0 through 4 correspond to Output Channels 0 through 4 respectively. Table 11. CDCE62005 Output Buffer Control Settings OUTPUT BUFFER CONTROL REGISTER n (n = 0,1,2,3,4) OUTPUT TYPE CMOSMODEnPX CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY OUTBUFSELnX OUTBUFSELnY n.22 n.23 n.24 n.25 n.26 n.27 0 0 0 0 0 1 LVPECL 0 1 0 1 1 1 LVDS See LVCMOS Output Buffer Configuration Settings 0 0 LVCMOS 0 1 0 1 1 0 Disabled to High-Z 8.3.5.9 Output Buffer Control – LVCMOS Configurations A LVCMOS output configuration requires additional configuration data. In the single ended configuration, each Output Channel provides a pair of outputs. The CDCE62005 supports four modes of operation for single ended outputs as listed in Table 12. Table 12. LVCMOS Output Buffer Configuration Settings OUTPUT BUFFER CONTROL – LVCMOS CONFIGURATION REGISTER n (n = 0,1,2,3,4) OUTPUT PIN OUTPUT MODE TYPE CMOSMODEnPX CMOSMODEnPY CMOSMODEnNX CMOSMODEnNY OUTBUFSELnX OUTBUFSELnY n.22 n.23 n.24 n.25 n.26 n.27 X X 0 0 0 0 LVCMOS Negative Active – Non-inverted X X 0 1 0 0 LVCMOS Negative Hi-Z X X 1 0 0 0 LVCMOS Negative Active – Non-inverted X X 1 1 0 0 LVCMOS Negative Low 0 0 X X 0 0 LVCMOS Positive Active – Non-inverted 0 1 X X 0 0 LVCMOS Positive Hi-Z 1 0 X X 0 0 LVCMOS Positive Active – Non-inverted 1 1 X X 0 0 LVCMOS Positive Low 28 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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