CDCE62005 datasheet(27/85 Pages) TI1

Part #	CDCE62005

Description	3:5 Clock Generator

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UxP

UxN

PRI_REF

SEC_REF

SMART _MUX

SYNTH

Sync

Pulse

Enable

LVDS

Clock Divider Module 0 - 4

LVPECL

Output

MUX

Control

Output Buffer Control

5

4

Registers 0 - 4

22 21

Registers 0 - 4

23

24

25

26

27

CDCE62005

www.ti.com

SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

The CDCE62005 Smart Multiplexer Block provides the ability to divide the primary and secondary UIB or to

disconnect a UIB from the first state of the smart multiplexer altogether.

Table 8. CDCE62005 Pre-Divider Settings

PRIMARY

SECONDARY

PRE-DIVIDER

BIT NAME

→

DIV2PRIY

DIV2PRIX

BIT NAME

→

DIV2SECY

DIV2SECX

DIVIDE

REGISTER.BIT

→

0.1

0.0

RATIO

REGISTER.BIT

→

1.1

1.0

RATIO

0

Hi-Z

0

Hi-Z

0

1

/2

0

1

/2

1

0

/1

1

0

/1

1

Reserved

1

Reserved

The CDCE62005 provides a Reference Divider that divides the clock exiting the first multiplexer stage; thus

dividing the primary (PRI_REF) or the secondary input (SEC_REF).

Table 9. CDCE62005 Reference Divider Settings

REFERENCE

DIVIDER

BIT NAME

→

REFDIV2

REFDIV1

REFDIV0

DIVIDE RATIO

REGISTER.BIT

→

3.0

2.1

2.0

0

/1

0

1

/2

0

1

0

/3

0

1

/4

1

0

/5

1

0

1

/6

1

0

/7

1

/8

8.3.5.6 Output Block

The output block includes five identical output channels. Each output channel comprises an output multiplexer, a

clock divider module, and a universal output buffer as shown in Figure 22.

Figure 22. CDCE62005 Output Channel

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