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CDCE62005 Datasheet(PDF) 26 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 85 page  /1:/2:HiZ /1:/2:HiZ Reference Divider /1 - /8 PRI_REF SEC_REF XTAL / AUX IN Smart MUX1 Smart MUX2 Smart MUX Control REF_SEL 1 0 Register 0 1 0 Register 1 Smart Multiplexer Auxiliary Input 0 1 0 Register 2 Register 3 Universal Input Buffers 5 4 3 2 Register 5 PRI _ REF SEC _ REF Internal ReferenceClock PrimaryClock SecondaryClock PrimaryClock CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com 8.3.5.4 Smart Multiplexer Auto Mode Smart Multiplexer Auto Mode switches automatically between clock inputs based on a prioritization scheme shown in Table 7. If using the Smart Multiplexer Auto Mode, the frequencies of the clock inputs may differ by up to 20%. The phase relationship between clock inputs has no restriction. Upon the detection of a loss of signal on the highest priority clock, the smart multiplex switches its output to the next highest priority clock on the first incoming rising edge of the next highest priority clock. During this switching operation, the output of the smart multiplexer is low. Upon restoration of the higher priority clock, the smart multiplexer waits until it detects four complete cycles from the higher priority clock prior to switching the output of the smart multiplexer back to the higher priority clock. During this switching operation, the output of the smart multiplexer remains high until the next falling edge as shown in Figure 20. Figure 20. CDCE62005 Smart Multiplexer Timing Diagram 8.3.5.5 Smart Multiplexer Dividers Figure 21. CDCE62005 Smart Multiplexer 26 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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