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CDCE62005 Datasheet(PDF) 24 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 85 page  Universal Input Control PN PP 6 1 0 Register 5 10 9 8 Register 6 12 7 SN SP PINV PRI_REF SINV SEC_REF 5.1 5.0 5.6 INBUFSELY INBUFSELX ACDCSEL 1 0 0 1.9V 1 0 1 1.2V 1 1 0 1.2V 1 1 1 1.2V Nominal Vbb Settings Vbb 1 mF Vbb 5.0 5.1 5.8, 6.12 5.9,5.10 INBUFSELX INBUFSELY TERMSEL INVBB P N INV 0 0 X X OFF OFF OFF X X 1 X OFF OFF OFF X 1 0 0 ON ON ON X 1 0 1 ON ON OFF SWITCH Status Settings 50 50 50 50 NOTE: 1.2 V is measured with a LVPECL current load and 0.95 V without any load. CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com 8.3.5.1 Universal Input Buffers (UIB) Figure 19 shows the key elements of a universal input buffer. A UIB supports multiple formats along with different termination and coupling schemes. The CDCE62005 implements the UIB by including on board switched termination, a programmable bias voltage generator, and an output multiplexer. The CDCE62005 provides a high degree of configurability on the UIB to facilitate most existing clock input formats. Figure 19. CDCE62005 Universal Input Buffer Switch PP and PN will be closed only if 5.8=0 and 5.0=1 or 5.1=1. Switch PINV will be closed only if 5.9=0 and switch SINV will be closed only if R5.10=0. Register 5.0 and 5.6 together pick the Vbb voltage. Table 5 lists several settings for many possible clock input scenarios. Note that the two universal input buffers share the Vbb generator. Therefore, if both inputs use internal termination, they must use the same configuration mode (LVDS, LVPECL, or LVCMOS). If the application requires different modes (for example, LVDS and LVPECL) then one of the two inputs must implement external termination. Table 5. CDCE62005 Universal Input Buffer Configuration Matrix PRI_REF CONFIGURATION MATRIX Register.Bit → 5.7 5.1 5.0 5.8 5.9 5.6 Bit Name → HYSTEN INBUFSELY INBUFSELX PRI_TERMSEL PRIINVBB ACDCSEL HYSTERESI MODE COUPLIN TERMINATIO Vbb S G N 1 0 0 X X X ENABLED LVCMOS DC N/A — 1 1 0 0 0 0 ENABLED LVPECL AC Internal 1.9V 1 1 0 0 0 1 ENABLED LVPECL DC Internal 1.2V(1) 1 1 0 1 X X ENABLED LVPECL — External — 1 1 1 0 0 0 ENABLED LVDS AC Internal 1.2V 1 1 1 0 0 1 ENABLED LVDS DC Internal 1.2V 1 1 1 1 X X ENABLED LVDS — External — 0 X X X X X OFF — — — — 1 X X X X X ENABLED — — — — (1) 0.95V unloaded 24 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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