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CDCE62005 Datasheet(PDF) 22 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 22 Page - Texas Instruments

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CDCE62005
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
www.ti.com
Table 4. CDCE62005 Device State Definitions
STATUS
STATE
DEVICE BEHAVIOR
ENTERED VIA
EXITED VIA
OUTPUT
OUTPUT
SPI PORT
PLL
DIVIDER
BUFFER
After device power supply reaches
Power applied to the device or upon exit
Power On Reset and EEPROM loading delays
OFF
Disabled
Disabled
OFF
approximately 2.35 V, the contents of
from Power Down State via the
are finished OR the Power_Down pin is set
Power-On
EEPROM are copied into the Device
Power_Down pin set HIGH.
LOW.
Reset
Registers within 100ns, thereby
initializing the device hardware.
The device waits until either
Delay process in the Power-On Reset
The device waits until either ENCAL_MODE
ON
Enabled
Disabled
OFF
ENCAL_MODE (Device Register 6 bit
State is finished or Sleep Mode (Sleep bit
(Device Register 6 bit 27) is low (Start up
27) is low (Start up calibration enabled)
is in Register 8 bit 7) is turned OFF while
calibration enabled) or both ENCAL_MODE is
Calibration
or both ENCAL_MODE is high (Manual
in the Sleep State. Power Down must be
high (Manual Calibration Enabled) AND ENCAL
Hold
Calibration Enabled) AND ENCAL
OFF to enter the Calibration Hold State.
(Device Register 6 bit 22) transitions from a low
(Device Register 6 bit 22) transitions
to a high signaling the device
from a low to a high signaling the
device.
Calibration Hold: CAL Enabled becomes
Calibration Process in completed
ON
Enabled
Disabled
OFF
true when either ENCAL_MODE (Device
Register 6 bit 27) is low or both
ENCAL_MODE is high AND ENCAL
The voltage controlled oscillator is
(Device Register 6 bit 22) transitions from
calibrated based on the PLL settings
a low to a high.
VCO CAL
and the incoming reference clock. After
Active Mode: A Manual Recalibration is
the VCO has been calibrated, the device
requested. This is initiated by setting
enters Active Mode automatically.
ENCAL_MODE to HIGH (Manual
Calibration Enabled) AND initiating a
calibration sequence by applying a LOW to
HIGH transition on ENCAL.
CAL Done (VCO calibration process
Sync, Power Down, Sleep, or Manual
ON
Enabled
Disabled or Enabled
HI-Z or Enabled
Active Mode
Normal Operation
finished) or Sync = OFF (from Sync State).
Recalibration activated.
Used to shut down all hardware and
Power_Down pin is pulled LOW.
Power_Down pin is pulled HIGH.
OFF
Disabled
Disabled
HI-Z
Resets the device after exiting the
Power Down State. Therefore, the
Power Down
EEPROM contents will eventually be
copied into RAM after the Power Down
State is exited.
Identical to the Power Down State
Sleep bit in device register 8 bit 7 is set
Sleep bit in device register 8 bit 7 is set HIGH.
ON
Disabled
Disabled
HI-Z
Sleep
except the EEPROM contents are not
LOW.
copied into RAM.
Sync synchronizes all output dividers so
Sync Bit in device register 8 bit 8 is set
Sync Bit in device register 8 bit 8 is set HIGH or
ON
Enabled
Disabled
HI-Z
that they begin counting at the same
LOW or Sync pin is pulled LOW
Sync pin is pulled HIGH
Sync
time. Note: this operation is performed
automatically each time a divider
register is accessed.
22
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