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CDCE62005 Datasheet(PDF) 19 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 19 Page - Texas Instruments |
19 / 85 page ![]() = ´ IN COMP F F R I = ´ ´ ´ OUT IN F F F R I O Output Divider0 U0P U0N Output Divider1 U1P U1N Output Divider2 U2P U2N Output Divider3 U3P U3N Output Divider4 U4P U4N PFD / CP /1:/2:HiZ Prescaler Feedback Divider Input Divider Reference Divider AUX OUT F IN EXT_LFP EXT_LFN F R I P O F OUT /1:/2:HiZ CDCE62005 www.ti.com SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 Functional Block Diagrams (continued) Figure 16. CDCE62005 Clock Path – Synthesizer Mode With respect to Figure 16, any output frequency generated by the CDCE62005 relates to the input frequency connected to the Synthesizer Block by Equation 1. (1) Equation 1 holds true when subject to the following constraints: 1.750 Ghz < O x P x FOUT< 2.356 GHz (2) The comparison frequency FCOMP is: 40 kHz ≤ FCOMP < 40 MHz (3) where: (4) NOTE This device cannot output the frequencies between 785 MHz to 875 MHz Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: CDCE62005 |
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