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CDCE62005 Datasheet(PDF) 18 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 18 Page - Texas Instruments |
18 / 85 page PFD / CP Prescaler /2,/3,/4,/5 Input Divider /1 - /256 SMART_MUX SYNTH /8 - /1280 Feedback Divider 1.750 GHz – 2.356 GHz Feedback Divider Feedback Bypass Divider /1, /2, /5, /8, /10, /16, /20 CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com Functional Block Diagrams (continued) 8.2.5 Synthesizer Block Figure 15 presents a high-level overview of the Synthesizer Block on the CDCE62005. Figure 15. CDCE62005 Synthesizer Block 8.2.6 Computing The Output Frequency Figure 16 shows the block diagram of the CDCE62005 in synthesizer mode highlighting the clock path for a single output. It also identifies the following regions containing dividers comprising the complete clock path • R: Includes the cumulative divider values of all dividers included from the Input Ports to the output of the Smart Multiplexer (see Input Block for more details) • O: The output divider value (see Figure 18 in Output Block for more details) • I: The input divider value (see Synthesizer Block for more details) • P: The prescaler divider value (see Synthesizer Block for more details) • F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for more details) 18 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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