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CDCE62005 Datasheet(PDF) 17 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
Download  85 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 17 Page - Texas Instruments

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OutputDivider(7-bits)
DigitalPhase Adjust(7-bits)
SyncPulse
(internallygenerated)
Enable
From
Output
MUX
To
Output
Buffer
/1,2,3,4,5
UxP
UxN
/1 - /8
/2
Digital Phase Adjust
(7 -bits )
PRI_REF
SEC_REF
SMART_MUX
SYNTH
Sync
Pulse
Enable
LVDS
Clock Divider Module 0 - 4
LVPECL
Output
MUX
Control
Output Buffer Control
CDCE62005
www.ti.com
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
Functional Block Diagrams (continued)
8.2.3 Output Block
Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a
universal output array as shown.
Figure 13. CDCE62005 Output Block (1 of 5)
8.2.4 Clock Divider Module 0–4
The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel
is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device
power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each
output. The output divider supports divide ratios from divide by 1 (bypass the divider) to divide by 80; the divider
does not support all integer values between 1 and 80. Refer to Table 13 for a complete list of divide ratios
supported.
Figure 14. CDCE62005 Output Divider Module (1 of 5)
Copyright © 2008–2015, Texas Instruments Incorporated
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