i

i

1

f

2 Z C

p

=

ƒ

1

2

3

4

5

6

GAIN/SLV

GVDD

INPL

INNL

AGND

PLIMIT

GND

20k

100k

1µF

R1

R2

TPA3131D2, TPA3132D2

SLOS841B – SEPTEMBER 2013 – REVISED JANUARY 2015

www.ti.com

Feature Description (continued)

Table 1. Gain and Master/Slave

MASTER / SLAVE

GAIN

R1 (to GND)

R2 (to GVDD)

INPUT IMPEDANCE

MODE

Master

20 dB

5.6 k

Ω

OPEN

60 k

Ω

Master

26 dB

20 k

Ω

100 k

Ω

30 k

Ω

Master

32 dB

39 k

Ω

100 k

Ω

15 k

Ω

Master

36 dB

47 k

Ω

75 k

Ω

9 k

Ω

Slave

20 dB

51 k

Ω

51 k

Ω

60 k

Ω

Slave

26 dB

75 k

Ω

47 k

Ω

30 k

Ω

Slave

32 dB

100 k

Ω

39 k

Ω

15 k

Ω

Slave

36 dB

100 k

Ω

16 k

Ω

9 k

Ω

Figure 19. Gain and Master/Slave Select Resistors

In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL

logic levels with compliance to GVDD.

7.3.2 Input Impedance

The TPA313xD2 input stage is a fully differential input stage and the input impedance changes with the gain

setting from 9 k

Ω at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The

tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 k

Ω. The inputs need to

be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-

ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter

with the following cut-off frequency:

(1)

If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. lists

the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10 times lower

capacitors can used – for example, a 1 µF can be used.

Table 2. Recommended Input AC-Coupling Capacitors

GAIN

INPUT IMPEDANCE

INPUT CAPACITANCE

HIGH-PASS FILTER

20 dB

60 k

Ω

1.5 µF

1.8 Hz

26 dB

30 k

Ω

3.3 µF

1.6 Hz

32 dB

15 k

Ω

5.6 µF

2.3 Hz

36 dB

9 k

Ω

10 µF

1.8 Hz

12

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