+

–

+

–

+

–

+

+

SDZ

MUTE

TTL

Buffer

Gain

Control

GAIN

OUTPR FB

RINN

RINP

Gain

Control

OUTPNR FB

FAULTZ

SYNC

GAIN/SLV

AM<2:0>

PLIMIT

AVCC

GVDD

LDO

Regulator

LINP

LINN

GND

Input

Sense

PBTL

Select

OUTPL_FB

Gain

Control

OUTNL_FB

AVDD

GVDD

PLIMIT

Reference

Ramp

Generator

Biases and

References

Startup Protection

Logic

SC Detect

DC Detect

Thermal

Detect

UVLO/OVLO

PVCC

GVDD

PVCC

Gate

Drive

OUTNL_

FB

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

PBTL Select

OUTPL_FB

GND

OUTPL

BSPL

GND

OUTNL

BSNL

GND

BSNR

OUTPR

GND

OUTNR

OUTNR_

FB

BSPR

OUTPR_FB

PVCC

GVDD

PVCC

Gate

Drive

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

PBTL Select

PLIMIT

PLIMIT

+

–

+

–

+

–

+

–

+

–

+

–

–

–

Thermal

Pad

TPA3131D2, TPA3132D2

www.ti.com

SLOS841B – SEPTEMBER 2013 – REVISED JANUARY 2015

7 Detailed Description

7.1 Overview

The TPA3132D2 device is a high-efficiency stereo Class-D audio power amplifier optimized for high-transient

power capability to utilize the dynamic power headroom of small loudspeakers. It’s capable of delivering high

peak power into a 4-

Ω speaker.

The device can be configured for either master or slave operation by using the SYNC pin. This helps to prevent

audible beats noise.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Gain Setting and Master and Slave

The gain of the TPA3131D2 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave

mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four

stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets

the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up

and cannot be changed while device is powered. shows the recommended resistor values and the state and

gain:

Copyright © 2013–2015, Texas Instruments Incorporated

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Product Folder Links: TPA3131D2 TPA3132D2