2

L

P

L

S

OUT

L

R

V

R + 2

R

P

=

for unclipped power

2

R

æ

ö

æ

ö

´

ç

÷

ç

÷

ç

÷

´

è

ø

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ø

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TPA3116D2-Q1, TPA3118D2-Q1

SLOS862A – JULY 2015 – REVISED AUGUST 2015

www.ti.com

The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum, or ceramic. If a

polarized type is used, the positive connection should face the input pins, which are biased to 3 Vdc.

7.3.3 Start-Up and Shutdown Operation

absolute minimum level for power conservation during periods of nonuse. The SD input pin should be held high

is in use. Pulling SD low sets the outputs to mute, and the amplifier enters a low-current state. It is not

recommended to leave SD unconnected, because amplifier operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power

supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is

selected and cannot be changed until the next power up.

7.3.4 PLIMIT Operation

The TPA311xD2-Q1 family has a built-in voltage limiter that can be used to limit the output voltage level below

the supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits

the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external

reference may also be used if tighter tolerance is required. Add a 1-µF capacitor from the PLIMIT pin to ground

to ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode.

Figure 14. Power Limit Example

The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle

to a fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply

connected to PVCC. This virtual rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage

can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.

where

•

•

•

•

•

(2)

12

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