+

–

+

–

+

–

+

+

SD

MUTE

TTL

Buffer

Gain

Control

GAIN

OUTPR_FB

RINP

RINN

Gain

Control

OUTPNR_FB

FAULT

SYNC

GAIN/SLV

AM<2:0>

PLIMIT

AVCC

GVDD

LDO

Regulator

LINP

LINN

GND

Input

Sense

PBTL

Select

OUTPL_FB

Gain

Control

OUTNL_FB

AVDD

GVDD

PLIMIT

Reference

Ramp

Generator

Biases and

References

Startup Protection

Logic

SC Detect

DC Detect

Thermal

Detect

UVLO/OVLO

PVCC

GVDD

PVCC

Gate

Drive

OUTNL_

FB

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

Modulation and

PBTL Select

OUTPL_FB

GND

OUTPL

BSPL

GND

OUTNL

BSNL

GND

BSNR

OUTPR

GND

OUTNR

OUTNR_

FB

BSPR

OUTPR_FB

PVCC

GVDD

PVCC

Gate

Drive

PVCC

GVDD

PVCC

Gate

Drive

PWM

Logic

Modulation and

PBTL Select

PLIMIT

PLIMIT

+

–

+

–

+

–

+

–

+

–

+

–

–

–

Thermal

Pad

+

–

PVCC

PVCC

TPA3116D2-Q1, TPA3118D2-Q1

SLOS862A – JULY 2015 – REVISED AUGUST 2015

www.ti.com

7 Detailed Description

7.1 Overview

The TPA311xD2-Q1 devices are highly efficient class-D audio amplifiers with integrated 120-m

Ω MOSFETs that

allow output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio

performance without the need for a bulky heat sink.

The device can be configured for either master or slave operation by using the SYNC pin. Doing so helps to

prevent audible beat noise.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Gain Setting and Master and Slave

The gain of the TPA311xD2-Q1 family is set by the voltage divider connected to the GAIN/SLV control pin.

Master or slave mode is also controlled by the same pin. An internal ADC is used to detect the eight input states.

The first four stages set the GAIN in master mode to gains of 20, 26, 32, and 36 dB, respectively, whereas the

next four stages set the GAIN in slave mode to gains of 20, 26, 32, and 36 dB, respectively. The gain setting is

latched during power up and cannot be changed while device is powered. Table 2 lists the recommended resistor

values and the state and gain.

10

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