PWM

Logic

Gate

Drive

Gate

Drive

PVCCL

PVCCL

GVDD

PVCCL

PVCCL

BSPL

PGND

OUTPL

OUTNL

PGND

GVDD

BSNL

PWM

Logic

Gate

Drive

Gate

Drive

PVCCL

PVCCL

GVDD

PVCCL

PVCCL

BSNR

PGND

OUTNR

OUTPR

PGND

GVDD

BSPR

LINP

LINN

RINP

RINN

UVLO/OVLO

SC Detect

DC Detect

Thermal

Detect

Startup Protection

Logic

Biases and

References

FAULT

SD

GAIN0

PLIMIT

AGND

AVCC

GAIN1

Gain

Control

TTL

Buffer

Ramp

Generator

AVDD

GVDD

GVDD

LDO

Regulator

Gain

Control

PLIMIT

PLIMIT

Reference

PBTL

Gain

Control

TTL

Buffer

PBTL

Select

PBTL Select

PBTL Select

OUTPL FB

OUTNL FB

OUTNN FB

OUTNP FB

OUTPR FB

OUTNR FB

OUTNL FB

OUTPL FB

PLIMIT

TPA3110D2-Q1

SLOS794B – SEPTEMBER 2012 – REVISED SEPTEMBER 2015

www.ti.com

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 DC Detect

TPA3110D2-Q1 has circuitry which protects the speakers from DC current which might occur due to defective

capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is reported on the

FAULT pin as a low state. The DC detect fault also causes the amplifier to shut down by changing the state of

the outputs to Hi-Z. To clear the DC detect it is necessary to cycle the PVCC supply. Cycling SD does NOT clear

a DC detect fault.

A DC detect fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example,

57%, –43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC

currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low

at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive

and negative inputs to avoid nuisance DC detect faults.

The minimum differential input voltages required to trigger the DC detect are shown in Table 1. The inputs must

remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.

14

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