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TPA3110D2-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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TPA3110D2-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 36 page  1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 SD FAULT LINP LINN GAIN0 GAIN1 AVCC AGND GVDD PLIMIT PVCCL PVCCL BSPL OUTPL PGND OUTNL BSNL BSNR OUTNR PGND RINN RINP NC 11 12 13 14 18 17 16 15 OUTPR BSPR PVCCR PVCCR PBTL TPA3110D2-Q1 www.ti.com SLOS794B – SEPTEMBER 2012 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions PWP Package 28-Pin HTSSOP With PowerPAD™ IC Package Top View Pin Functions PIN TYPE DESCRIPTION NO. NAME Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL 1 SD I logic levels with compliance to AVCC. Open drain output used to display short circuit or DC detect fault status. Voltage compliant to 2 FAULT O AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and DC detect faults must be reset by cycling PVCC. 3 LINP I Positive audio input for left channel, biased at 3 V. 4 LINN I Negative audio input for left channel, biased at 3 V. 5 GAIN0 I Gain select least significant bit, TTL logic levels with compliance to AVCC. 6 GAIN1 I Gain select most significant bit, TTL logic levels with compliance to AVCC. 7 AVCC P Analog supply 8 AGND — Analog signal ground, connect to the thermal pad. High-side FET gate drive supply. The nominal voltage is 7 V. GVDD should also be used as 9 GVDD O a supply for the PLIMIT function. Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. 10 PLIMIT I Connect directly to GVDD for no power limit. 11 RINN I Negative audio input for right channel, biased at 3 V. 12 RINP I Positive audio input for right channel, biased at 3 V. 13 NC — Not connected 14 PBTL I Parallel BTL mode switch Power supply for right channel H-bridge. Right channel and left channel power supply inputs 15 PVCCR P are connect internally. Power supply for right channel H-bridge. Right channel and left channel power supply inputs 16 PVCCR P are connect internally. 17 BSPR I Bootstrap I/O for right channel, positive high-side FET 18 OUTPR O Class-D H-bridge positive output for right channel 19 PGND — Power ground for the H-bridges 20 OUTNR O Class-D H-bridge negative output for right channel 21 BSNR I Bootstrap I/O for right channel, negative high-side FET 22 BSNL I Bootstrap I/O for left channel, negative high-side FET 23 OUTNL O Class-D H-bridge negative output for left channel 24 PGND — Power ground for the H-bridges 25 OUTPL O Class-D H-bridge positive output for left channel 26 BSPL I Bootstrap I/O for left channel, positive high-side FET Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPA3110D2-Q1 |
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