LINP

LINN

FAULT

GAIN0

GAIN1

PLIMIT

RINN

RINP

PBTL

FB

FB

FB

FB

OUTPL

OUTNL

FB

OUTNR

FB

OUTPR

`

Top Layer Ground Plane

Vias on the thermal pad to get

optimal thermal performance

1 µF

1 nF

100 µF

0.1 nF

1 nF

100 µF

0.1 nF

1 nF

1 nF

1 nF

1 nF

330 pF

330 pF

0.22 µF

0.22 µF

0.22 µF

0.22 µF

330 pF

330 pF

10

SD

10

10

10

1 µF

1 µF

1 µF

1 µF

1 µF

Place Decoupling capacitors as

close to the device as possible.

Place Decoupling

capacitors as close to

the device as possible.

Several Via connection

between top and

bottom ground layers

for EMI and Thermal

performance

Bulk Capacitor for good

audio decoupling close to

Power source

Pad to Top Layer Ground Plane

Top Layer Traces

PowerPAD

Via to Ground Plane

Via to Power

TPA3110D2

www.ti.com

SLOS528E – JULY 2009 – REVISED NOVEMBER 2015

Layout Guidelines (continued)

ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1

μF and

1

μF also of good quality to the PVCC connections at each end of the chip.

•

Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to

PGND as small and tight as possible. The size of this current loop determines its effectiveness as an

antenna.

•

Grounding—The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The

PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be

connected at the thermal pad, which should be used as a central ground connection or star ground for the

TPA3110D2.

•

Output filter—The ferrite EMI filter (Figure 39) should be placed as close to the output terminals as possible

for the best EMI performance. The LC filter (Figure 37 and Figure 38) should be placed close to the outputs.

The capacitors used in both the ferrite and LC filters should be grounded to power ground.

•

Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal

reliability. The dimensions of the thermal pad and thermal land should be 6.46mm by 2.35mm. Seven rows of

solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the

thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom

layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application

Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB

footprints, see figures at the end of this data sheet.

For an example layout, see the TPA3110D2 Evaluation Module (TPA3110D2EVM) User Manual. Both the EVM

user manual and the thermal pad application report are available on the TI Web site at www.ti.com.

12.2 Layout Example

Figure 47. TPA3110D2 PCB Layout

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