L

P

L

S

OUT

L

2

R

x V

R + 2 x R

P

=

for unclipped power

2 x R

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TPA3110D2

SLOS528E – JULY 2009 – REVISED NOVEMBER 2015

www.ti.com

The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle

to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply

connected to PVCC. This "virtual" rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to

calculate the maximum output power for a given maximum input voltage and speaker impedance.

Where:

•

•

•

•

(1)

Table 2. PLIMIT Typical Operation

OUTPUT VOLTAGE

TEST CONDITIONS

PLIMIT VOLTAGE

OUTPUT POWER (W)

PVCC=24V, Vin=1Vrms,

6.97

36.1 (thermally limited)

43

RL=8

Ω, Gain=26dB

PVCC=24V, Vin=1Vrms,

2.94

15

25.2

RL=8

Ω, Gain=26dB

PVCC=24V, Vin=1Vrms,

2.34

10

20

RL=8

Ω, Gain=26dB

PVCC=24V, Vin=1Vrms,

1.62

5

14

RL=8

Ω, Gain=26dB

PVCC=24V, Vin=1Vrms,

6.97

12.1

27.7

RL=8

Ω, Gain=20dB

PVCC=24V, Vin=1Vrms,

3.00

10

23

RL=8

Ω, Gain=20dB

PVCC=24V, Vin=1Vrms,

1.86

5

14.8

RL=8

Ω, Gain=20dB

PVCC=12V, Vin=1Vrms,

6.97

10.55

23.5

RL=8

Ω, Gain=20dB

PVCC=12V, Vin=1Vrms,

1.76

5

15

RL=8

Ω, Gain=20dB

9.3.5 GVDD Supply

The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply

the PLIMIT voltage divider circuit. Add a 1-

μF capacitor to ground at this pin.

9.3.6 PBTL Select

TPA3110D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly. If

the PBTL pin (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are

synchronized and in phase. To operate in this PBTL (mono) mode, apply the input signal to the RIGHT input and

place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for

best efficiency. The voltage slew rate of the PBTL pin must be restricted to no more than 10V/ms. For higher

slew rates, use a 100k

Ω resistor in series with the terminals. For an example of the PBTL connection, see the

schematic in the APPLICATION INFORMATION section.

For normal BTL operation, connect the PBTL pin to local ground.

18

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