TPA3110D2PowerLimitFunction

Vin=1.13

Freq=1kHzRLoad=8W

VPP

PLIMIT =1.8VPout=5W

PLIMIT =3VPout=10W

PLIMIT =6.96VPout=11.8W

Vinput

TPA3110D2

www.ti.com

SLOS528E – JULY 2009 – REVISED NOVEMBER 2015

Feature Description (continued)

The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside

are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance

from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.

For design purposes, the input network (discussed in the next section) should be designed assuming an input

impedance of 7.2 k

Ω, which is the absolute minimum input impedance of the TPA3110D2. At the lower gain

settings, the input impedance could increase as high as 72 k

Ω

Table 1. Gain Setting

INPUT IMPEDANCE

AMPLIFIER GAIN (dB)

(k

Ω)

GAIN1

GAIN0

TYP

TYP

0

0

20

60

0

1

26

30

1

0

32

15

1

1

36

9

9.3.3 Differential Inputs

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To

use the TPA3110D2 with a differential source, connect the positive lead of the audio source to the INP input and

the negative lead from the audio source to the INN input. To use the TPA3110D2 with a single-ended source, ac

ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply

the audio source to either input. In a single-ended input application, the unused input should be ac grounded at

the audio source instead of at the device input for best noise performance. For good transient performance, the

impedance seen at each of the two differential inputs should be the same.

The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to

allow the input dc blocking capacitors to become completely charged during the 14 ms power-up time. If the input

capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching

which can result in pop if the input components are not well matched.

9.3.4 PLIMIT

The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail.

Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also

be used if tighter tolerance is required. Also add a 1

μF capacitor from pin 10 to ground.

Figure 40. PLIMIT Circuit Operation

Copyright © 2009–2015, Texas Instruments Incorporated

Submit Documentation Feedback

17

Product Folder Links: TPA3110D2