PGA2311

SBOS218B – DECEMBER 2001 – REVISED JANUARY 2016

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Feature Description (continued)

7.3.5 MUTE Function

Muting can be achieved by either hardware or software control. Hardware muting is accomplished through the

MUTE input, and software muting by loading all zeroes into the volume control register.

k

Ω resistors to ground. The mute is activated with a zero crossing detection (independent of the zero cross

enable status), or an 16-ms time-out to eliminate any audible clicks or pops. MUTE also initiates an internal

offset calibration.

A software mute is implemented by loading all zeroes into the volume control register. The internal amplifier is

set to unity gain, with the amplifier input connected to AGND.

7.4 Device Functional Modes

7.4.1 Power

−Up State

On power up, power

−up reset is activated for about 100 ms, during which the circuit is in hardware MUTE state

and all internal flip-flops are reset. At the end of this period, the offset calibration is initiated without any external

or the software MUTE condition. The gain remains at this setting until the host controller programs new settings

for for each channel via the serial control port.

If the power supply voltage drops below ±3.2 V during normal operation, the circuit enters a hardware MUTE

state. A power-up sequence initiates if the power supply voltage returns to greater than ±3.2 V.

7.5 Programming

The serial control port is used to program the gain settings for the PGA2311. The serial control port includes

three input pins and one output pin. The inputs include CS (pin 2), SDI (pin 3), and SCLK (pin 6). The sole output

pin is SDO (pin 7).

The CS pin functions as the chip select input. Data may be written to the PGA2311 only when CS is LOW. SDI is

the serial data input pin. Control data is provided as a 16-bit word at the SDI pin, 8 bits each for the left and right

channel gain settings.

Data is formatted as MSB first, in straight binary code. SCLK is the serial clock input. Data is clocked into SDI on

the rising edge of SCLK.

SDO is the serial data output pin, and used when daisy-chaining multiple PGA2311 devices. Daisy-chain

operation is described in Daisy-Chaining Multiple PGA2311 Devices. SDO is a tri-state output, and assumes a

high impedance state when CS is HIGH.

The protocol for the serial control port is shown in Figure 1. See Figure 2 for detailed timing specifications for the

serial control port.

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