SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

t

(BUF)

S

S

P

P

INA3221

SBOS576A – MAY 2012 – REVISED JUNE 2013

www.ti.com

When the bus is idle, the SDA and SCL lines are pulled high by the pull-up devices. The master generates a

start condition followed by a valid serial byte with the High-Speed (HS) master code 00001XXX. This

transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA3221

does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 3.4-

MHz operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission

speeds up to 3.4 MHz are allowed. Instead of using a stop condition, repeated start conditions should be used to

secure the bus in HS-mode. A stop condition ends the HS-mode and switches all internal INA3221 filters to

support F/S mode.

Figure 33. Bus Timing Diagram

Bus Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL operating frequency

0.001

0.4

0.001

3.4

MHz

Bus free time between stop and start

600

160

ns

conditions

Hold time after repeated START condition.

100

100

ns

After this period, the first clock is generated.

Repeated start condition setup time

100

100

ns

STOP condition setup time

100

100

ns

Data hold time

0

0

ns

Data setup time

100

10

ns

SCL clock low period

1300

160

ns

SCL clock high period

600

60

ns

Clock and data fall time

300

160

ns

Clock and data rise time

300

160

ns

Clock and data rise time for SCLK

≤ 100 kHz

1000

ns

SMBus ALERT RESPONSE

The INA3221 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response

provides a quick fault identification for simple slave devices. When an Alert occurs, the master can broadcast the

Alert Response slave address (0001 100) with the R/W bit set high. Following this Alert Response, any slave

devices that generated an alert identify themselves by acknowledging the Alert Response and sending their

respective address on the bus.

more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an

Acknowledge and continues to hold the Alert line low until the interrupt is cleared.

32

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