DAC8812

SBAS349C – AUGUST 2005 – REVISED NOVEMBER 2015

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Device Functional Modes (continued)

Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data

setup and data hold time requirements specified in the Interface Timing specifications of the Electrical

Characteristics. Data can only be clocked in while the CS chip select pin is active low. For the DAC8812, only

the last 18 bits clocked into the serial register are interrogated when the CS pin returns to the logic high state.

Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the

DAC8812. Keeping the CS line low between the first, second, and third byte transfers will result in a successful

serial register update.

Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new

data to the target DAC register, determined by the decoding of address bits A1 and A0. For the DAC8812,

Table 1, Table 2, Table 3, and Figure 1 define the characteristics of the software serial interface.

B17

B0

Bit

(MSB)

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

(LSB)

Data

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

(1)

Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line positive edge returns to

logic high. At this point an internally-generated load strobe transfers the serial register data contents (bits D15-D0) to the decoded DAC-

input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8812 shift register are ignored; only the last 18

bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.

CS

CLK

LDAC

RS

MSB

SERIAL SHIFT REGISTER

INPUT REGISTER

DAC REGISTER

H

X

H

H

X

No effect

Latched

Latched

L

L

H

H

X

No effect

Latched

Latched

L

↑+

H

H

X

Shift register data advanced one bit

Latched

Latched

L

H

H

H

X

No effect

Latched

Latched

↑+

L

H

H

X

No effect

Selected DAC updated with current SR contents

Latched

H

X

L

H

X

No effect

Latched

Transparent

H

X

H

H

X

No effect

Latched

Latched

H

X

↑+

H

X

No effect

Latched

Latched

H

X

H

L

0

No effect

Latched data = 0000h

Latched data = 0000h

H

X

H

L

H

No effect

Latched data = 8000h

Latched data = 8000h

(1)

↑+ = Positive logic transition; X = Don't care

Table 3. Address Decode

A1

A0

DAC DECODE

0

0

None

0

1

DAC A

1

0

DAC B

1

1

DAC A and DAC B

16

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