250 W

DGND

DIGITAL

INPUTS

V

DD

16

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A0

A1

A

B

DAC

Decode

Input

Register R

Input

Register R

DACA

Register R

DACB

Register R

DAC A

DAC B

Set

MSB

Power-

on

Reset

DGND

MSB

LDAC

RS

V

DD

CS

CLK

SDI

V

AB

REF

I

A

OUT

A

A

GND

R B

FB

I

B

OUT

A

B

GND

EN

Set

MSB

R B

FB

DAC8812

www.ti.com

SBAS349C – AUGUST 2005 – REVISED NOVEMBER 2015

Figure 32. System-Level Digital Interfacing

8.3.2 Power-On Reset

2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place.

8.3.2.1 ESD Protection Circuits

shown in Figure 33.

Figure 33. Equivalent ESD Protection Circuits

8.4 Device Functional Modes

8.4.1 Serial Data Interface

The DAC8812 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8812 is

clocked into the serial input register in an 18-bit data-word format. MSB bits are loaded first. Table 1 defines the

18 data-word bits for the DAC8812.

Copyright © 2005–2015, Texas Instruments Incorporated

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