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DAC8812 Datasheet(PDF) 6 Page - Texas Instruments |
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DAC8812 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 29 page DAC8812 SBAS349C – AUGUST 2005 – REVISED NOVEMBER 2015 www.ti.com Electrical Characteristics (continued) VDD = 2.7 V to 5.5 V, IOUTX = Virtual GND, AGNDX = 0 V, VREFA, B = 10 V, TA = full operating temperature range, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY CHARACTERISTICS VDD RANGE Power supply range 2.7 5.5 V Logic inputs = 0 V, VDD = 4.5 V to 5.5 V 2 5 μA IDD Positive supply current Logic inputs = 0 V, VDD = 2.7 V to 3.6 V 1 2.5 μA PDISS Power dissipation Logic inputs = 0 V 0.0275 mW PSS Power supply sensitivity ΔVDD = ±5% 0.006% AC CHARACTERISTICS(2) (3) To ±0.1% of full-scale, 0.3 Data = 0000h to FFFFh to 0000h ts Output voltage settling time µs To ±0.0015% of full-scale, 0.5 Data = 0000h to FFFFh to 0000h QG DAC glitch impulse VREFx = 10 V, data = 7FFFh to 8000h to 7FFFh 5 nV-s BW –3 dB Reference multiplying BW VREFx = 100 mVRMS, data = FFFFh, CFB = 3 pF 10 MHz Data = 0000h, VREFx = 100 mVRMS, Feedthrough error –70 dB f = 100 kHz Data = 0000h, VREFB = 100 mVRMS, Crosstalk error –100 dB Adjacent channel, f = 100 kHz QD Digital feedthrough CS = 1 and fCLK = 1 MHz 1 nV-s THD Total harmonic distortion VREF = 5 VPP, data = FFFFh, f = 1 kHz –105 dB en Output spot noise voltage f = 1 kHz, BW = 1 Hz 12 nV/ √Hz (3) All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier. 7.6 Timing Requirements See Figure 1 MIN NOM MAX UNIT INTERFACE TIMING(1) tCH Clock duration, high 10 ns tCL Clock duration, low 10 ns tCSS CS to clock setup 0 ns tCSH Clock to CS hold 10 ns tLDAC Load DAC pulse duration 20 ns tDS Data setup 10 ns tDH Data hold 10 ns tLDS Load setup 5 ns tLDH Load hold 25 ns (1) All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 7.7 Switching Characteristics over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERFACE TIMING tPD Clock to SDO propagation delay 2 20 ns 6 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: DAC8812 |
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