MC145151–2 through MC145158–2

MOTOROLA

28

DESIGN CONSIDERATIONS

PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN

C)

_

+

A

C

R2

C

VCO

C

VCO

R2

B)

A)

C

VCO

PDout

PDout

φR —

φV —

PDout —

φR

φV

R1

R1

R1

R1

R2

filter

φV and φR. The value of CC should be such that the corner frequency of this network does not significantly affect ωn.

The

φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the

op amp used in the combiner/loop filter.

DEFINITIONS:

N = Total Division Ratio in feedback loop

K

K

KVCO (VCO Gain) =

2

π∆fVCO

∆VVCO

2

πfr

10

(at phase detector input).

Damping Factor:

RECOMMENDED READING:

Gardner, Floyd M.,

Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.

Manassewitsch, Vadim,

Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.

Blanchard, Alain,

Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.

Egan, William F.,

Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.

Rohde, Ulrich L.,

Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.

Berlin, Howard M.,

Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.

Kinley, Harold,

The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.

AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.

AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from

Electronic Design,

1987.

φR —

φV —

F(s) =

ASSUMING GAIN A IS VERY LARGE, THEN:

F(s) =

ζ =

ωn =

NR1C

R1sC + 1

ωn =

ζ =

ωnR2C

2

R2sC + 1

R1sC

1

N

ωn

2K

φKVCO

F(s) =

ζ =

ωn =

(R1 + R2)sC + 1

R2sC + 1

NC(R1 + R2)

R2C +

N

K

φKVCO

K

φKVCO

NCR1

0.5

ωn

K

φKVCO

K

φKVCO