MC145151–2 through MC145158–2

MOTOROLA

27

Symbol

Parameter

Test Condition

VDD

V

– 40

°C

25

°C

85

°C

Unit

Symbol

Parameter

Test Condition

VDD

V

Min

Max

Min

Max

Min

Max

Unit

fi

Input Frequency

(fin, OSCin)

R

≥ 8, A ≥ 0, N ≥ 8

Vin = 500 mV p–p

ac coupled sine wave

3

5

9

—

—

—

6

15

15

—

—

—

6

15

15

—

—

—

6

15

15

MHz

R

≥ 8, A ≥ 0, N ≥ 8

Vin = 1 V p–p ac coupled

sine wave

3

5

9

—

—

—

12

22

25

—

—

—

12

20

22

—

—

—

7

20

22

MHz

R

≥ 8, A ≥ 0, N ≥ 8

Vin = VDD to VSS

dc coupled square wave

3

5

9

—

—

—

13

25

25

—

—

—

12

22

25

—

—

—

8

22

25

MHz

NOTE: Usually, the PLL’s propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency limit of the system.

The upper frequency limit is found with the following formula: f = P / (tP + tset) where f is the upper frequency in Hz, P is the lower of the dual

modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and tset is the prescaler setup time in seconds.

For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup time is 16 ns. Thus, if the 64/65

ratio is utilized, the upper frequency limit is f = P / (tP + tset) = 64/(70 + 16) = 744 MHz.

VH = High Voltage Level.

VL = Low Voltage Level.

* At this point, when both fR and fV are in phase, the output is forced to near mid–supply.

NOTE: The PDout generates error pulses during out–of–lock conditions. When locked in phase and frequency the output is high

and the voltage at this pin is determined by the low–pass filter capacitor.

fR

REFERENCE

OSC

÷ R

fV

FEEDBACK

(fin ÷ N)

PDout

φR

φV

LD

*

VH

VL

VH

VL

VH

HIGH IMPEDANCE

VH

VL

VH

VL

VH

VL

VL

Figure 9. Phase Detector/Lock Detector Output Waveforms