 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MC145151P2 Datasheet(PDF) 15 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
MC145151P2 Datasheet(HTML) 15 Page - Motorola, Inc |
|
|
15 / 36 page  MC145151–2 through MC145158–2 MOTOROLA 15 OUTPUT PINS PDout Phase Detector A Output (Pin 6) Three–state output of phase detector for use as loop–error signal. Double–ended outputs are also available for this pur- pose (see φV and φR). Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High–Imped- ance State φR, φV Phase Detector B Outputs (Pins 4, 3) These phase detector outputs can be combined externally for a loop–error signal. A single–ended output is also avail- able for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by φV pulsing low. φR remains essentially high. If the frequency fV is less than fR or if the phase of fV is lagging, then error information is provided by φR pulsing low. φV remains essentially high. If the frequency of fV = fR and both are in phase, then both φV and φR remain high except for a small minimum time period when both pulse low in phase. MC Dual–Modulus Prescale Control Output (Pin 8) Signal generated by the on–chip control logic circuitry for controlling an external dual–modulus prescaler. The MC level will be low at the beginning of a count cycle and will remain low until the ÷ A counter has counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N counter has counted the rest of the way down from its programmed value (N – A additional counts since both ÷ N and ÷ A are counting down during the first por- tion of the cycle). MC is then set back low, the counters preset to their respective programmed values, and the above sequence repeated. This provides for a total programmable divide value (NT) = N P + A where P and P + 1 represent the dual–modulus prescaler divide values respectively for high and low MC levels, N the number programmed into the ÷ N counter, and A the number programmed into the ÷ A counter. LD Lock Detector Output (Pin 9) Essentially a high level when loop is locked (fR, fV of same phase and frequency). LD pulses low when loop is out of lock. SW1, SW2 Band Switch Outputs (Pins 14, 15) SW1 and SW2 provide latched open–drain outputs corre- sponding to data bits numbers one and two. These outputs can be tied through external resistors to voltages as high as 15 V, independent of the VDD supply voltage. These are typically used for band switch functions. A logic 1 causes the output to assume a high–impedance state, while a logic 0 causes the output to be low. REFout Buffered Reference Oscillator Output (Pin 17) Buffered output of on–chip reference oscillator or exter- nally provided reference–input signal. POWER SUPPLY VDD Positive Power Supply (Pin 5) The positive power supply potential. This pin may range from + 3 to + 9 V with respect to VSS. VSS Negative Power Supply (Pin 7) The most negative supply potential. This pin is usually ground. |
Similar Part No. - MC145151P2 |
|
Similar Description - MC145151P2 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
