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MC145151P2 Datasheet(PDF) 14 Page - Motorola, Inc |
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MC145151P2 Datasheet(HTML) 14 Page - Motorola, Inc |
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14 / 36 page  MC145151–2 through MC145158–2 MOTOROLA 14 12 x 8 ROM REFERENCE DECODER φV φR 12–BIT ÷ R COUNTER PHASE DETECTOR B PHASE DETECTOR A LOCK DETECT LD PDout fin VDD OSCin OSCout ENB 12 10 SW2 SW1 fR fV LATCH DATA 2–BIT SHIFT REGISTER CLK 10 REFout 10–BIT SHIFT REGISTER 7–BIT SHIFT REGISTER ÷ A COUNTER LATCH ÷ N COUNTER LATCH 7–BIT ÷ A COUNTER 10–BIT ÷ N COUNTER CONTROL LOGIC MC 7 7 MC145156–2 BLOCK DIAGRAM RA2 RA0 RA1 PIN DESCRIPTIONS INPUT PINS fin Frequency Input (Pin 10) Input to the positive edge triggered ÷ N and ÷ A counters. fin is typically derived from a dual–modulus prescaler and is ac coupled into the device. For larger amplitude signals (standard CMOS logic levels), dc coupling may be used. RA0, RA1, RA2 Reference Address Inputs (Pins 20, 1, 2) These three inputs establish a code defining one of eight possible divide values for the total reference divider, as defined by the table below: Reference Address Code Total Divide Value RA2 RA1 RA0 Divide Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 64 128 256 640 1000 1024 2048 CLK, DATA Shift Register Clock, Serial Data Inputs (Pins 11, 12) Each low–to–high transition clocks one bit into the on–chip 19–bit shift register. The data input provides programming in- formation for the 10–bit ÷ N counter, the 7–bit ÷ A counter, and the two switch signals SW1 and SW2. The entry format is as follows: ÷ N COUNTER BITS LAST DATA BIT IN (BIT NO. 19) FIRST DATA BIT IN (BIT NO. 1) ÷ A COUNTER BITS ENB Latch Enable Input (Pin 13) When high (1), ENB transfers the contents of the shift reg- ister into the latches, and to the programmable counter in- puts, and the switch outputs SW1 and SW2. When low (0), ENB inhibits the above action and thus allows changes to be made in the shift register data without affecting the counter programming and switch outputs. An on–chip pull–up esta- blishes a continuously high level for ENB when no external signal is applied. ENB is normally low and is pulsed high to transfer data to the latches. OSCin, OSCout Reference Oscillator Input/Output (Pins 19, 18) These pins form an on–chip reference oscillator when con- nected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as the input for an externally–gener- ated reference signal. This signal is typically ac coupled to OSCin, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSCout. TEST Factory Test Input (Pin 16) Used in manufacturing. Must be left open or tied to VSS. |
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