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MT8870 Datasheet(PDF) 10 Page - Mitel Networks Corporation |
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MT8870 Datasheet(HTML) 10 Page - Mitel Networks Corporation |
10 / 12 page MT8870D/MT8870D-1 ISO2-CMOS 4-20 ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. *NOTES: 1. Used for guard-time calculation purposes only. 2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are recommendations based upon network requirements. 3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high. Figure 10 - Single-Ended Input Configuration AC Electrical Characteristics - V DD=5.0V±5%, VSS=0V, -40°C ≤ To ≤ +85°C , using Test Circuit shown in Figure 10. Characteristics Sym Min Typ‡ Max Units Conditions 1 T I M I N G Tone present detect time tDP 5 11 14 ms Note 1 2 Tone absent detect time tDA 0.5 4 8.5 ms Note 1 3 Tone duration accept tREC 40 ms Note 2 4 Tone duration reject tREC 20 ms Note 2 5 Interdigit pause accept tID 40 ms Note 2 6 Interdigit pause reject tDO 20 ms Note 2 7 O U T P U T S Propagation delay (St to Q) tPQ 811 µsTOE=VDD 8 Propagation delay (St to StD) tPStD 12 16 µsTOE=VDD 9 Output data set up (Q to StD) tQStD 3.4 µsTOE=VDD 10 Propagation delay (TOE to Q ENABLE) tPTE 50 ns load of 10 k Ω, 50 pF 11 Propagation delay (TOE to Q DISABLE) tPTD 300 ns load of 10 k Ω, 50 pF 12 P D W N Power-up time tPU 30 ms Note 3 13 Power-down time tPD 20 ms 14 C L O C K Crystal/clock frequency fC 3.5759 3.5795 3.5831 MHz 15 Clock input rise time tLHCL 110 ns Ext. clock 16 Clock input fall time tHLCL 110 ns Ext. clock 17 Clock input duty cycle DCCL 40 50 60 % Ext. clock 18 Capacitive load (OSC2) CLO 30 pF IN+ IN- GS VRef INH PDWN OSC 1 OSC 2 VSS TOE VDD St/GT ESt StD Q4 Q3 Q2 Q1 DTMF Input C1 R1 R2 X-tal VDD C2 R3 NOTES: R1,R2=100KΩ ± 1% R3=300KΩ ± 1% C1,C2=100 nF ± 5% X-tal=3.579545 MHz ± 0.1% MT8870D/MT8870D-1 |
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