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MT8870 Datasheet(PDF) 2 Page - Mitel Networks Corporation

Part # MT8870
Description  ISO2-CMOS Integrated DTMF Receiver
Download  12 Pages
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Manufacturer  MITEL [Mitel Networks Corporation]
Direct Link  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT8870 Datasheet(HTML) 2 Page - Mitel Networks Corporation

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MT8870D/MT8870D-1 ISO2-CMOS
4-12
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
18
20
11
IN+
Non-Inverting Op-Amp (Input).
2
2
IN-
Inverting Op-Amp (Input).
33
GS
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44
VRef
Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 6
and Fig. 10).
55
INH
Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
66
PWDN
Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
78
OSC1
Clock (Input).
89
OSC2
Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
910
VSS
Ground (Input). 0V typical.
10
11
TOE
Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
11-
14
12-
15
Q1-Q4
Three State Data (Output). When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15
17
StD
Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below VTSt.
16
18
ESt
Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
17
19
St/GT
Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18
20
VDD
Positive power supply (Input). +5V typical.
7,
16
NC
No Connection.
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
18 PIN CERDIP/PLASTIC DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
20 PIN SSOP/TSSOP
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
NC


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