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NOA1305CUTAG Datasheet(PDF) 3 Page - ON Semiconductor |
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NOA1305CUTAG Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 13 page NOA1305 http://onsemi.com 3 Table 3. OPERATING RANGES Rating Symbol Standard Mode Fast Mode Unit Min Max Min Max Power supply voltage VDD 2.4 3.6 2.4 3.6 V Power supply current IDD 120 120 mA Quiescent supply current (Note 3) IDD_qe 2.0 2.0 mA Low level input voltage (VDD related input levels) VIL −0.5 0.3 VDD −0.5 0.3 VDD V High level input voltage (VDD related input levels) (Note 4) VIH 0.7 VDD VDD + 0.5 0.7 VDD VDD + 0.5 V Hysteresis of Schmitt trigger inputs (VDD > 2 V) Vhys N/A N/A 0.05 VDD − V Low level output voltage (open drain) at 3 mA sink current (VDD > 2 V) VOL 0 0.4 0 0.4 V Output low current (VOl=0.4 V) IOL 3 N/A 3 N/A mA Output low current (VOl=0.6 V) IOL N/A N/A 6 N/A mA Output fall time from VIHmin to VILmax with a bus capacit- ance, Cb from 10 pF to 400 pF (Note 4) tof − 250 20+0.1Cb 250 ns Pulse width of spikes which must be suppressed by the input filter tSP N/A N/A 0 50 ns Input current of IO pin with an input voltage between 0.1 VDD and 0.9 VDD II −10 10 −10 10 mA Capacitance on IO pin CI − 10 − 10 pF Operating free−air temperature range TA −40 85 −40 85 °C 3. Current dissipation when a software Power Down command is sent to the device. 4. Cb = capacitance of one bus line, maximum value of which including all parasitic capacitances should be less than 400 pF. Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over VDD = 3.3 V, −40°C < TA < 85°C) (Note 5) Parameter Symbol Standard Mode Fast Mode Unit Min Max Min Max SCL clock frequency fSCL 0 100 0 400 kHz Hold time for START condition. After this period, the first clock pulse is generated. tHD;STA 4.0 − 0.6 − mS Low period of SCL clock tLOW 4.7 1.3 mS High period of SCL clock tHIGH 4.0 0.6 mS Set−up time for a repeated START condition tSU;STA 4.7 − 0.6 − mS Data hold time for I2C−bus devices tHD;DAT_d 0 3.45 0 0.9 mS Data set−up time tSU;DAT 250 − 100 − nS Rise time of both SDA and SCL (Note 6) tr − 1000 20 + 0.1Cb 300 nS Fall time of both SDA and SCL (Note 6) tf − 300 20 + 0.1Cb 300 nS Set−up time for STOP condition tSU;STO 4.0 − 0.6 − mS Bus free time between STOP and START condition tBUF 4.7 − 1.3 − mS Capacitive load for each bus line Cb − 400 − 400 pF Noise margin at the low level for each connected device (including hysteresis) VnL 0.1 VDD − 0.1 VDD − V Noise margin at the high level for each connected device (including hysteresis) VnH 0.2 VDD − 0.2 VDD − V Parameter Symbol Typ Typ Unit Internal Oscillator Frequency fosc 1 1 MHz 5. Refer to Figure 3 for more information on AC characteristics 6. The rise time and fall time are measured with a pull−up resistor Rp = 1 kW and Cb of 400 pF (including all parasitic capacitances). |
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