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LC88FC2H0B Datasheet(PDF) 31 Page - ON Semiconductor |
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LC88FC2H0B Datasheet(HTML) 31 Page - ON Semiconductor |
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31 / 47 page  LC88FC2H0B www.onsemi.com 31 5-2. SMIIC1 I 2C Mode Input/Output Characteristics Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD [V] Min typ max unit Period tSCL SM1CK (PB4) See Fig. 8. 2.7 to 3.6 5 Tfilt Low level pulse width tSCLL 2.5 High level pulse width tSCLH 2 Period tSCLx SM1CK (PB4) Specified as interval up to time when output state starts changing. 2.7 to 3.6 10 Low level pulse width tSCLLx 1/2 tSCL High level pulse width tSCLHx 1/2 SM0CK and SM0DA pins input spike suppression time tsp SM1CK (PB4) SM1DA (PB5) See Fig. 8. 2.7 to 3.6 1 Tfilt Bus release time between start and stop tBUF SM1CK (PB4) SM1DA (PB5) See Fig. 8. 2.7 to 3.6 2.5 Tfilt tBUFx SM1CK (PB4) SM1DA (PB5) Standard clock mode Specified as interval up to time when output state starts changing. 5.5 μsec High-speed clock mode Specified as interval up to time when output state starts changing. 1.6 Start/restart condition hold time tHD;STA SM1CK (PB4) SM1DA (PB5) When SMIIC register control bit, I2CSHDS=0 See Fig. 8. 2.7 to 3.6 2.0 Tfilt When SMIIC register control bit I2CSHDS=1 See Fig. 8. 2.5 tHD;STAx SM1CK (PB4) SM1DA (PB5) Standard clock mode Specified as interval up to time when output state starts changing. 4.1 μsec High-speed clock mode Specified as interval up to time when output state starts changing. 1.0 Restart condition setup time tSU;STA SM1CK (PB4) SM1DA (PB5) See Fig. 8. 2.7 to 3.6 1.0 Tfilt tSU;STAx SM1CK (PB4) SM1DA (PB5) Standard clock mode Specified as interval up to time when output state starts changing. 5.5 μsec High-speed clock mode Specified as interval up to time when output state starts changing. 1.6 |
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