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LC88FC2H0B Datasheet(PDF) 29 Page - ON Semiconductor |
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LC88FC2H0B Datasheet(HTML) 29 Page - ON Semiconductor |
29 / 47 page ![]() LC88FC2H0B www.onsemi.com 29 Parameter Symbol Applicable Pin/Remarks Conditions Specification VDD [V] Min typ max Unit Stop condition setup time tSU;STO SM0CK (P22) SM0DA (P23) See Fig. 8. 2.7 to 3.6 1.0 Tfilt tSU;STOx SM0CK (P22) SM0DA (P23) Standard clock mode Specified as interval up to time when output state starts changing. 4.9 s High-speed clock mode Specified as interval up to time when output state starts changing. 1.1 Data hold time tHD;DAT SM0CK (P22) SM0DA (P23) See Fig. 8. 2.7 to 3.6 0 Tfilt tHD;DATx SM0CK (P22) SM0DA (P23) Specified as interval up to time when output state starts changing. 1 1.5 Data setup time tSU;DAT SM0CK (P22) SM0DA (P23) See Fig. 8. 2.7 to 3.6 1 Tfilt tSU;DATx SM0CK (P22) SM0DA (P23) Specified as interval up to time when output state starts changing. 1tSCL- 1.5Tfilt SM0CK and SM0DA pins fall time tF SM0CK (P22) SM0DA (P23) See Fig. 8. 2.7 to 3.6 300 ns tF SM0CK (P22) SM0DA (P23) When SMIIC register control bits PSLW=1, P5V=1 3 20+0.1Cb 250 SM0CK, SM0DA port output FAST mode Cb ≤ 400pF 3.0 to 3.6 100 Note 4-8-1 : These specifications are theoretical values. Add margin depending on its use. Note 4-8-2 : The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC 1 0 1 tCYC 2 1 0 tCYC 3 1 1 tCYC 4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range : 250 ns ≥ Tfilt > 140 ns Note 4-8-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400 pF Note 4-8-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows : 250 ns ≥ Tfilt > 140 ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100 kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows : 250 ns ≥ Tfilt > 140 ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400 kHz |
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