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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

©2001, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

READ/WRITE TIMING

WRITE

D(A1)

123

456789

CLK

t KHKH

10

CE#

R/W#

CKE#

BWx#

ADV/LD#

ADDRESS

A1

A2

A3

A4

A5

A6

A7

DQ

COMMAND

D(A1)

D(A2)

D(A5)

Q(A4)

Q(A3)

D(A2+1)

WRITE

D(A2)

BURST

WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OE#

DON’T CARE

UNDEFINED

Q(A6)

Q(A4+1)

NOTE: 1. For this waveform, ZZ is tied LOW.

2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.

3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

-6

-7.5

-10

SYM

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

3.5

4.2

5.0

ns

1.5

1.7

2.0

ns

1.5

1.7

2.0

ns

1.5

1.7

2.0

ns

1.5

1.7

2.0

ns

0.5

0.5

0.5

ns

0.5

0.5

0.5

ns

0.5

0.5

0.5

ns

0.5

0.5

0.5

ns

READ/WRITE TIMING PARAMETERS

-6

-7.5

-10

SYM

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

6.0

7.5

10

ns

166

133

100

MHz

1.7

2.0

3.2

ns

1.7

2.0

3.2

ns

3.5

4.2

5.0

ns

1.5

1.5

1.5

ns

1.5

1.5

1.5

ns

1.5

3.5

1.5

3.5

1.5

3.5

ns

3.5

4.2

5.0

ns

0

0

0

ns