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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

©2001, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

NOTE: 1. This parameter is sampled.

2. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for

turnaround timing.

4. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is

defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.

6. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.

7. This parameter is sampled.

8. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.

9. Transition is measured ±200mV from steady state voltage.

10. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when they are being registered into the device. All other synchronous inputs must meet the setup and hold times

with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each

rising edge of CLK when ADV/LD# is LOW to remain enabled.

11. Preliminary package data.

AC ELECTRICAL CHARACTERISTICS

(Notes 2, 3, 4) (0°C

≤ T

-6

-7.5

-10

DESCRIPTION

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Clock

Clock cycle time

6.0

7.5

10

ns

Clock frequency

166

133

100

MHz

Clock HIGH time

1.7

2.0

3.2

ns

5

Clock LOW time

1.7

2.0

3.2

ns

5

Output Times

Clock to output valid

3.5

4.2

5.0

ns

Clock to output invalid

1.5

1.5

1.5

ns

6

Clock to output in Low-Z

1.5

1.5

1.5

ns

6, 7, 8, 9

Clock to output in High-Z

1.5

3.5

1.5

3.5

1.5

3.5

ns

6, 7, 8, 9

OE# to output valid

3.5

4.2

5.0

ns

2

OE# to output in Low-Z

0

0

0

ns

6, 7, 8, 9

OE# to output in High-Z

3.5

4.2

5.0

ns

6, 7, 8, 9

Setup Times

Address

1.5

1.7

2.0

ns

10

Clock enable (CKE#)

1.5

1.7

2.0

ns

10

Control signals

1.5

1.7

2.0

ns

10

Data-in

1.5

1.7

2.0

ns

10

Hold Times

Address

0.5

0.5

0.5

ns

10

Clock enable (CKE#)

0.5

0.5

0.5

ns

10

Control signals

0.5

0.5

0.5

ns

10

Data-in

0.5

0.5

0.5

ns

10

FBGA THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Junction to Ambient

Test conditions follow standard test methods

θ

JA

40

°C/W

1, 11

(Airflow of 1m/s)

and procedures for measuring thermal

Junction to Case (Top)

impedance, per EIA/JESD51.

θ

JC

9

°C/W

1, 11

Junction to Pins (Bottom)

θ

JB

17

°C/W

1, 11