MT55L512L18P datasheet(21/30 Pages) MICRON

Part #	MT55L512L18P

Description	8Mb ZBT SRAM

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Manufacturer	MICRON [Micron Technology]

Direct Link	http://www.micron.com

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21

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

NOTE: 1. VDDQ = +3.3V ±0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O

configuration.

2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device

is active (not in deselected mode).

4. Typical values are measured at +3.3V, +25°C and 10ns cycle time.

5. This parameter is sampled.

IDD OPERATING CONDITIONS AND MAXIMUM LIMITS

(Note 1) (0°C

≤ T

A ≤ +70°C; VDD = +3.3V ±0.165V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-6

-7.5

-10

UNITS NOTES

Power Supply

Device selected; All inputs

≤ VIL

Current: Operating

or

≥ VIH; Cycle time ≥ tKC (MIN);

IDD

200

500

400

300

m A

2, 3, 4

VDD = MAX; Outputs open

Power Supply

Device selected; VDD = MAX;

Current: Idle

CKE#

≥ VIH;IDD1

10

25

20

m A

2, 3, 4

All inputs

≤ VSS + 0.2 or ≥ VDD - 0.2;

Cycle time

≥ tKC (MIN)

CMOS Standby

Device deselected; VDD = MAX;

All inputs

≤ VSS + 0.2 or ≥ VDD - 0.2;

ISB2

0.5

10

m A

3, 4

All inputs static; CLK frequency = 0

TTL Standby

Device deselected; VDD = MAX;

All inputs

≤ VIL or ≥ VIH;ISB3

6

252525

m A

3, 4

All inputs static; CLK frequency = 0

Clock Running

Device deselected; VDD = MAX;

ADV/LD#

≥ VIH; All inputs ≤ VSS + 0.2

ISB4

45

120

75

60

m A

3, 4

or

≥ VDD - 0.2; Cycle time ≥ tKC (MIN)

Snooze Mode

ZZ

≥ VIH

ISB2Z

0.5

10

m A

4

MAX

TQFP THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Thermal Resistance

Test conditions follow standard test methods

θ

JA

40

°C/W

5

(Junction to Ambient)

and procedures for measuring thermal

Thermal Resistance

impedance, per EIA/JESD51.

θ

JC

8

°C/W

5

(Junction to Top of Case)

BGA THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Junction to Ambient

Test conditions follow standard test methods

θ

JA

40

°C/W

5

(Airflow of 1m/s)

and procedures for measuring thermal

Junction to Case (Top)

impedance, per EIA/JESD51.

θ

JC

9

°C/W

5

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