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MT55L512L18P Datasheet(PDF) 19 Page - Micron Technology |
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MT55L512L18P Datasheet(HTML) 19 Page - Micron Technology |
19 / 30 page ![]() 19 8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_2.p65 – Rev. 6/01 ©2001, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS ................................... -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS ....................................... -0.5V to VDD VIN -0.5V to VDDQ + 0.5V Storage Temperature (plastic) .......... -55°C to +150°C Storage Temperature (FBGA) .......... -55°C to +125°C Junction Temperature** .................................. +150°C Short Circuit Output Current .......................... 100mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow. See Micron Technical Note TN-05-14 for more information. 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C ≤ T A ≤ +70°C; VDD, VDDQ = +3.3V ±0.165V unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH 2.0 VDD + 0.3 V 1, 2 Input High (Logic 1) Voltage DQ pins VIH 2.0 VDD + 0.3 V 1, 2 Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2 Input Leakage Current 0V ≤ VIN ≤ VDD ILI -1.0 1.0 µA 3 Output Leakage Current Output(s) disabled, ILO -1.0 1.0 µA 0V ≤ VIN ≤ VDD Output High Voltage IOH = -4.0mA VOH 2.4 – V 1, 4 Output Low Voltage IOL = 8.0mA VOL – 0.4 V 1, 4 Supply Voltage VDD 3.135 3.465 V 1 Isolated Output Buffer Supply VDDQ 3.135 VDD V 1, 5 NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA Undershoot: VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA Power-up: VIH ≤ +3.465V and VDD ≤ +3.135V for t ≤ 200ms 3. MODE pin has an internal pull-up, and input leakage = ±10µA. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply. |
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