18

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

©2001, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

TRUTH TABLE

(Notes 5-10)

ADDRESS

ADV/

OPERATION

USED

C E # CE2# C E 2 Z Z

L D # R/W# B W x O E # CKE# C L K

D Q

NOTES

DESELECT Cycle

None

H

X

X

L

L

X

X

X

L

L-H High-Z

DESELECT Cycle

None

X

H

X

L

L

X

X

X

L

L-H High-Z

DESELECT Cycle

None

X

X

L

L

L

X

X

X

L

L-H High-Z

CONTINUE DESELECT Cycle

None

X

X

X

L

H

X

X

X

L

L-H High-Z

1

READ Cycle

External

L

L

H

L

L

H

X

L

L

L-H

Q

(Begin Burst)

READ Cycle

Next

X

X

X

L

H

X

X

L

L

L-H

Q

1, 11

(Continue Burst)

NOP/DUMMY READ

External

L

L

H

L

L

H

X

H

L

L-H High-Z

2

(Begin Burst)

DUMMY READ

Next

X

X

X

L

H

X

X

H

L

L-H High-Z

1, 2,

(Continue Burst)

11

WRITE Cycle

External

L

L

H

L

L

L

L

X

L

L-H

D

3

(Begin Burst)

WRITE Cycle

Next

X

X

X

L

H

X

L

X

L

L-H

D

1, 3,

(Continue Burst)

11

NOP/WRITE ABORT

None

L

L

H

L

L

L

H

X

L

L-H High-Z

2, 3

(Begin Burst)

WRITE ABORT

Next

X

X

X

L

H

X

H

X

L

L-H High-Z

1, 2,

(Continue Burst)

3, 11

IGNORE CLOCK EDGE

Current

X

X

X

L

X

X

X

X

H

L-H

–

4

(Stall)

SNOOZE MODE

None

X

X

X

H

X

X

X

X

X

X

High-Z

NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle

is executed first.

2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.

A WRITE ABORT means a WRITE command is given, but no operation is performed.

3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off

the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an

application’s requirements.

4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it

occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE

CLOCK EDGE cycle.

5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,

BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.

6. BWa# enables WRITEs to Byte “a” (DQa pins); BWb# enables WRITEs to Byte “b” (DQb pins); BWc# enables WRITEs to

Byte “c” (DQc pins); BWd# enables WRITEs to Byte “d” (DQd pins).

7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

8. Wait states are inserted by setting CKE# HIGH.

9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.

11. The address counter is incremented for all CONTINUE BURST cycles.