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8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

©2001, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

STATE DIAGRAM FOR ZBT SRAM

DESELECT

BEGIN

READ

BURST

READ

BEGIN

WRITE

DS

DS

DS

BURST

WRITE

READ

DS

WRITE

WRITE

BURST

READ

WRITE

READ

BURST

BURST

READ

BURST

KEY:

COMMAND

DS

READ

WRITE

BURST

OPERATION

DESELECT

New READ

New WRITE

BURST READ,

BURST WRITE or

CONTINUE DESELECT

BURST

READ

WRITE

NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the

clock (CLK) input and does not change the state of the device.

2. States change on the rising edge of the clock (CLK).