16

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

©2001, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

FUNCTION

R/W#

BWa#

BWb#

BWc#

BWd#

READ

H

X

X

X

X

WRITE Byte “a”

LL

H

H

H

WRITE Byte “b”

LHLH

H

WRITE Byte “c”

LH

HL

H

WRITE Byte “d”

L

HHH

L

WRITE All Bytes

LLLL

L

WRITE ABORT/NOP

L

H

H

H

H

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)

NOTE: Using R/W# and byte write(s), any one or more bytes may be written.

FUNCTION

R/W#

BWa#

BWb#

READ

H

X

X

WRITE Byte “a”

LL

H

WRITE Byte “b”

LHL

WRITE All Bytes

L

L

L

WRITE ABORT/NOP

L

H

H

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)

NOTE: Using R/W# and byte write(s), any one or more bytes may be

written.