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MT55L512L18P Datasheet(PDF) 12 Page - Micron Technology |
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MT55L512L18P Datasheet(HTML) 12 Page - Micron Technology |
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12 / 30 page  12 8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. MT55L512L18P_2.p65 – Rev. 6/01 ©2001, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 PIPELINED ZBT SRAM PIN LAYOUT (TOP VIEW) 119-PIN BGA x18 x32/x36 NOTE: 1. Pin 4A is reserved for address expansion to 18Mb. 2. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 3. Pin 3J, 5J, and 5R do not have to be connected directly to VDD if the input voltage is ≥ VIH. A B C D E F G H J K L M N P R T U 1 VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ SA CE2 SA NC DQb NC DQb NC VDD DQb NC DQb NC DQPb SA SA DNU SA SA SA VSS VSS VSS BWb# VSS VDD3 VSS VSS VSS VSS VSS MODE (LBO#) SA DNU NF1 ADV/LD# VDD NC CE# OE# (G#) SA R/W# VDD CLK NC CKE# SA1 SA0 VDD NC DNU SA SA SA VSS VSS VSS VSS VSS VDD3 VSS BWa# VSS VSS VSS VDD 3 SA DNU SA CE2# SA DQPa NC DQa NC DQa VDD NC DQa NC DQa NC SA SA NC VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ TOP VIEW 234567 A B C D E F G H J K L M N P R T U 1 VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ SA CE2 SA NC/DQPc2 DQc DQc DQc DQc VDD DQd DQd DQd DQd NC/DQPd2 SA NC DNU SA SA SA VSS VSS VSS BWc# VSS VDD3 VSS BWd# VSS VSS VSS MODE (LBO#) SA DNU NF1 ADV/LD# VDD NC CE# OE# (G#) SA R/W# VDD CLK NC CKE# SA1 SA0 VDD SA DNU SA SA SA VSS VSS VSS BWb# VSS VDD3 VSS BWa# VSS VSS VSS VDD 3 SA DNU SA CE2# SA NC/DQPb2 DQb DQb DQb DQb VDD DQa DQa DQa DQa NC/DQPa2 SA NC NC VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ TOP VIEW 234567 |
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