9

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L512L18P_2.p65 – Rev. 6/01

©2001, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

FBGA PIN DESCRIPTIONS

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

6R

6R

SA0

Input

Synchronous Address Inputs: These inputs are registered and

6P

6P

SA1

must meet the setup and hold times around the rising edge of

2A, 9A, 10A, 2A, 9A, 10A,

SA

CLK.

11A, 2B, 10B,

2B, 10B,

3P, 4P, 8P,

3P, 4P, 8P,

9P, 10P, 3R,

9P, 10P, 3R,

4R, 8R, 9R,

4R, 8R, 9R,

10R, 11R

10R, 11R

5B

5B

BWa#

Input

Synchronous Byte Write Enables: These active LOW inputs allow

4A

5A

BWb#

individual bytes to be written and must meet the setup and hold

–

4A

BWc#

times around the rising edge of CLK. A byte write enable is LOW

–

4B

BWd#

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.

For the x32 and x36 versions, BWa# controls DQa’s and DQPa;

BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;

BWd# controls DQd’s and DQPd. Parity is only available on the

x18 and x36 versions.

7A

7A

CKE#

Input

Synchronous Clock Enable: This active LOW input permits CLK to

propogate throughout the device. When CKE# is HIGH, the

device ignores the CLK input and effectively internally extends

the previous CLK cycle. This input must meet the setup and hold

times around the rising edge of CLK.

7B

7B

R/W#

Input

Read/Write: This input determines the cycle type when ADV/LD#

is LOW and is the only means for determining READs and

WRITEs. READ cycles may not be converted into WRITEs (and vice

versa) other than by loading a new address. A LOW on this pin

permits BYTE WRITE operations to meet the setup and hold times

around the rising edge of CLK. Full bus-width WRITEs occur if all

byte write enables are LOW.

6B

6B

CLK

Input

Clock: This signal registers the address, data, chip enable, byte

write enables and burst control inputs on its rising edge. All

synchronous inputs must meet setup and hold times around the

clock’s rising edge.

3A

3A

CE#

Input

Synchronous Chip Enable: This active LOW input is used to enable

the device. CE# is sampled only when a new external address is

loaded.

6A

6A

CE2#

Input

Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

11H

11H

ZZ

Input

Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in

the memory array is retained. When ZZ is active, all other inputs

are ignored.

3B

3B

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to

enable the device and is sampled only when a new external

address is loaded.

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